1. Field
The following description relates to a verification supporting apparatus and a verification supporting method of a reconfigurable processor.
2. Description of Related Art
A Coarse-Grained Array (CGA)-based reconfigurable processor has a complicated structure that includes function units (FUs), a global register file, a local register file, and other components that would be known to one of ordinary skill in the art. Thus, detecting locations and time points at which a CGA executes erroneous computation is a difficult and lengthy process.
An error verification apparatus has been developed to find locations and time points at which a CGA has executed erroneous computation that is incorrect. The CGA-based reconfigurable processor is based on modulo-scheduling such that the prologue, body, and epilogue of a loop have the same configuration. Accordingly, invalid operations (that is, operations having a negative influence on the results of computation) may be executed in the prologue and epilogue of the loop. However, due to execution of the invalid operations, the error verification apparatus may output verification results that are erroneous.